How Computer Memory (RAM) Actually Works

The Speed-Capacity Paradox

In How a CPU Executes an Instruction, we traced how a processor’s Arithmetic Logic Unit executes instructions in fractions of a nanosecond.

Inside the CPU core are registers: tiny storage bins made of logic gates located directly beside the arithmetic units. Registers are unimaginably fast: they can be read or written within a single clock tick ($<0.3\text{ nanoseconds}$).

               THE MEMORY HIERARCHY LATENCY PYRAMID

                        ┌───────────┐
                        │ REGISTERS │  ◄── ~1 KB, < 0.5 ns access
                        └─────┬─────┘
                              │
                       ┌──────┴──────┐
                       │  SRAM CACHE │  ◄── L1/L2/L3: 32 KB to 64 MB, 1–10 ns
                       └──────┬──────┘
                              │
                    ┌─────────┴─────────┐
                    │     DRAM (RAM)    │  ◄── 16 GB to 128 GB, 50–80 ns
                    └─────────┬─────────┘
                              │
               ┌──────────────┴──────────────┐
               │    NON-VOLATILE SSD / DISK  │  ◄── 1 TB to 4 TB, 10,000–50,000 ns
               └─────────────────────────────┘

However, a CPU register file holds only a few thousand bits of data.

At the other extreme sits your Solid State Drive (SSD). An SSD can store terabytes of photos, videos, and operating system binaries, and it remembers that data even when you unplug the power cord. But an SSD is excruciatingly slow from the CPU’s perspective: accessing an SSD takes between $10,000$ and $50,000\text{ nanoseconds}$.

If a CPU had to fetch every instruction and operand directly from an SSD, a 4.0 GHz processor would spend 99.99% of its life doing nothing, frozen in a state of idle starvation waiting for disk controllers.

Humanity solved this dilemma by building a middle tier: Dynamic Random Access Memory (DRAM).

RAM is large enough to hold billions of bytes of active operating system code, browser tabs, and application heaps, yet fast enough to deliver data to the CPU in roughly $50\text{ to }70\text{ nanoseconds}$.

The word Random Access means that any individual byte in a 32-gigabyte memory module can be accessed in virtually the exact same amount of time, regardless of whether that byte is located at the physical beginning, middle, or end of the silicon chip—unlike magnetic tape or spinning platters which required mechanical seeking.

Yet RAM has an astonishing physical property that puzzles most people: The moment you turn off the computer, every single byte of data in RAM disappears instantly into thin air.

Why is RAM volatile? Why can't it remember its data like an SSD?

To understand why, you must look inside a single microscopic memory cell.

The 1T1C Cell: A Transistor and a Leaking Bucket

In 1968, an IBM researcher named Robert H. Dennard patented an invention that changed digital computing forever: the One-Transistor One-Capacitor (1T1C) Dynamic RAM cell.

Dennard asked a radical question: What is the absolute minimum amount of physical hardware required to store one binary bit of information?

His answer was a masterclass in minimalist physics:

1. One microscopic capacitor to store an electrostatic charge.
2. One access transistor (a MOSFET) to act as a gate connecting the capacitor to a data wire.

                  THE CLASSICAL 1T1C DRAM BIT CELL

                         Wordline (Row Select: Gate Voltage)
                                       │
                                       ▼
                             ┌─────────────────┐
                             │  Access MOSFET  │
        Bitline ─────────────┤                 ├──────────────┐
     (Data Column Wire)      └─────────────────┘              │
                                                              ▼
                                                     ┌─────────────────┐
                                                     │ Microscopic     │
                                                     │ Capacitor (C_s) │
                                                     │ (~30 femto-     │
                                                     │  farads)        │
                                                     └────────┬────────┘
                                                              │
                                                             GND

A capacitor is simply two conductive plates separated by an insulating dielectric material:

• When the capacitor is charged with electrons, it represents a binary 1.
• When the capacitor is drained of electrons, it represents a binary 0.

How Small Is a Memory Capacitor?

In a modern DDR4 or DDR5 memory chip, the capacitor in a DRAM cell has a capacitance of roughly 25 to 35 femtofarads ($1\text{ femtofarad} = 10^{-15}\text{ Farads}$).

At a operating voltage of $1.1\text{ Volts}$, a charged capacitor holds only about 200,000 electrons!

Because space on a silicon chip is at an extreme premium, these capacitors cannot be laid flat across the silicon surface. In modern manufacturing, they are constructed as microscopic vertical cylinders etched deep into the silicon—called trench capacitors or towering stack capacitors.

These vertical pillars are over 100 times taller than they are wide, resembling microscopic microscopic skyscrapers rising from the silicon substrate.

The "Dynamic" Curse: The Leaking Bucket

A physical capacitor is not a sealed glass jar. It is an electrostatic bucket made of atoms.

The insulating dielectric layer between the capacitor plates is only a few atoms thick. Furthermore, the access transistor connected to it is not an ideal switch; even when turned OFF, silicon transistors suffer from quantum subthreshold leakage current.

Electrons inevitably leak out:

• Through the gate dielectric of the transistor.
• Across the reverse-biased P-N junction into the silicon substrate.
• Through dielectric relaxation in the capacitor itself.

                  THE LEAKAGE RACE AGAINST TIME

      Initial Full Charge (Logical 1)          Leaked State (Data Corruption!)
      
         ┌───────────────────────┐                ┌───────────────────────┐
         │ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ │                │                       │
         │ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ │ ──Leakage──► │                       │
         │ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ ⚡ │ (~64 ms)     │   ⚡   ⚡              │
         └───────────────────────┘                └───────────────────────┘
          Full Voltage: V_DD (~1.1V)               Voltage drops below V_ref;
          Unambiguous '1'                          Sense amp reads as '0'!

A fully charged DRAM capacitor leaks its charge away within 64 milliseconds ($0.064\text{ seconds}$).

If left alone, every binary 1 in your computer would decay into a binary 0 in less than a tenth of a second. The entire operating system would dissolve into digital garbage.

This is why it is called Dynamic RAM. Unlike Static RAM (SRAM), which holds its data indefinitely as long as electricity is applied, DRAM is constantly dying.

To keep data alive, the memory controller must perform an endless task: The Refresh Cycle.

Every 64 milliseconds (or 32 milliseconds at higher temperatures), the memory controller pauses and systematically reads every single row of memory and writes the charge right back in, topping up the leaking buckets before they drop below the threshold of detection.

In a modern computer with 32 gigabytes of RAM, billions of capacitors are refreshed thousands of times per second. Up to 5% of a computer's total memory bandwidth is consumed simply by this desperate, unceasing choreography to prevent its own memory from evaporating.

The Memory Grid: Wordlines and Bitlines

You cannot connect two dedicated wires to every one of 32 billion capacitors. If you did, a RAM stick would require 64 billion copper pins.

Instead, DRAM cells are organized into an immense two-dimensional Cartesian matrix of Rows and Columns:

                     THE 2D DRAM CELL ARRAY MATRIX

                       Bitline 0     Bitline 1     Bitline 2
                           │             │             │
        Wordline 0 ────────┼─────────────┼─────────────┼───────
                     [1T1C Cell]   [1T1C Cell]   [1T1C Cell]
                           │             │             │
        Wordline 1 ────────┼─────────────┼─────────────┼───────
                     [1T1C Cell]   [1T1C Cell]   [1T1C Cell]
                           │             │             │
        Wordline 2 ────────┼─────────────┼─────────────┼───────
                     [1T1C Cell]   [1T1C Cell]   [1T1C Cell]
                           │             │             │
                           ▼             ▼             ▼
                      [Sense Amp]   [Sense Amp]   [Sense Amp]

• Wordlines (Rows): Horizontal copper wires that connect to the gate terminals of all access transistors in a given row.
• Bitlines (Columns): Vertical copper wires that connect to the data terminals of all access transistors in a given column.

To read or write data, the memory controller splits a memory address into two halves:

1. Row Address: Activates a specific horizontal Wordline, turning on thousands of access transistors simultaneously.
2. Column Address: Selects which vertical Bitlines to route out to the memory bus pins.

The Destructive Read and the Sense Amplifier

When you read a bit from a DRAM cell, you run headfirst into a fundamental law of electrostatics: conservation of charge.

The vertical bitline wire is long and has its own parasitic capacitance ($C_{\text{bitline}} \approx 300\text{ fF}$)—roughly ten times larger than the tiny storage capacitor ($C_s \approx 30\text{ fF}$).

Before a read begins, the bitline is precharged to exactly half of the supply voltage:

$$V_{\text{precharge}} = \frac{V_{DD}}{2} \quad (\approx 0.55\text{ V})$$

When the Wordline goes HIGH, the access transistor turns ON. The tiny storage capacitor is now connected directly to the long, heavy bitline wire.

The charges mix:

• If the cell held a Logical 1 ($1.1\text{ V}$), a tiny burst of electrons flows out of the cell onto the bitline. The bitline voltage nudges up by a microscopic amount: roughly $\mathbf{+50\text{ millivolts}}$.
• If the cell held a Logical 0 ($0.0\text{ V}$), electrons flow from the bitline into the cell. The bitline voltage drops by roughly $\mathbf{-50\text{ millivolts}}$.

Notice what just happened: The act of reading the cell completely destroyed the data stored inside it! The capacitor discharged its electrons onto the bitline. If the process stopped here, the bit would be gone forever. This is called a Destructive Read.

The Rescue: The Differential Sense Amplifier

At the bottom of each column sits a Sense Amplifier: a high-speed, cross-coupled analog inverter circuit.

The sequence diagram below illustrates the exact cycle through which data is read, amplified, and restored:

The sense amplifier compares the bitline voltage against an untouched reference line sitting at exactly $V_{DD}/2$.

When it detects that the bitline has nudged even $+50\text{ mV}$ above reference, an internal positive-feedback loop triggers:

1. It immediately pulls the bitline all the way up to full rail voltage ($+V_{DD} = 1.1\text{ V}$).
2. Because the access transistor is still open, that full $1.1\text{ V}$ surges straight back into the tiny storage capacitor!
3. The capacitor is completely recharged back to 100%.

The sense amplifier does double duty: it reads the microscopic signal and simultaneously restores the destroyed data back into the cell before the wordline closes.

SRAM vs. DRAM: The Speed vs. Density Tradeoff

If DRAM is so leaky, destructive, and complicated, why do we use it? Why not build all computer memory out of static logic circuits?

Inside the CPU core, engineers do exactly that. They use Static RAM (SRAM) for L1, L2, and L3 caches.

                 SRAM CELL (6T) vs. DRAM CELL (1T1C)

       SRAM (Static RAM: 6 Transistors)         DRAM (Dynamic RAM: 1T1C)
       
              +V_DD        +V_DD
                │            │                        Wordline
           ┌────┴───┐    ┌───┴────┐                      │
           │  PMOS  │    │  PMOS  │                      ▼
           └────┬───┘    └───┬────┘               ┌──────────────┐
       BL ──┤ NMOS  ├──┬─┤  NMOS ├── BL           │Access MOSFET │
            └───┬───┘  │ └───┬────┘         BL ───┤              ├──[Capacitor]
               GND     └─────┘ GND                └──────────────┘      │
                                                                       GND
        • 6 transistors per bit                  • 1 transistor + 1 capacitor
        • Zero leakage; no refresh needed        • Leaks constantly; needs refresh
        • Ultra-fast: ~1 nanosecond              • Modest: ~50 nanoseconds
        • Physically massive footprint           • Microscopic footprint

Look at the difference:

• SRAM: Uses a bistable flip-flop circuit made of 6 transistors (6T). It holds its state purely through cross-coupled logic feedback. It never leaks, never needs a refresh cycle, and does not suffer from destructive reads. It responds in less than 1 nanosecond. But because it requires 6 large transistors per bit, it consumes enormous physical silicon area. If you tried to build 32 gigabytes of SRAM, the chip would be the size of a dinner plate and cost thousands of dollars.
• DRAM: Uses only 1 transistor and 1 capacitor (1T1C). It is over six times smaller per bit than SRAM. You can pack billions of DRAM cells into a tiny square of silicon costing a few dollars.

We accept the complexity of leakage and refresh because DRAM gives us unbeatable physical density at low cost.

What Memory Timings (CAS Latency) Actually Mean

When you buy computer memory, you see specifications like:

$$\text{DDR4-3200 CL16} \quad \text{or} \quad \text{DDR5-6000 CL32}$$

What does CL16 or CL32 actually mean in physical hardware?

CL stands for Column Address Strobe (CAS) Latency. It is the number of clock cycles that elapse between the moment the memory controller requests a specific column of data and the moment that data physically appears on the output pins.

The physical steps of a DRAM access are bound by strict physical time limits:

When you calculate the absolute physical time in nanoseconds:

$$\text{Latency (ns)} = \frac{\text{CAS Cycles}}{\text{Clock Frequency (GHz)}} \approx 10\text{ to }14\text{ nanoseconds}$$

Despite three decades of memory evolution—from original SDRAM in 1997 to cutting-edge DDR5 today—the physical time it takes a capacitor to dump its charge into a sense amplifier and restore itself has remained virtually constant at roughly 10 to 15 nanoseconds.

What increased by a factor of 100 was not the fundamental capacitor physics, but the bandwidth of the bus: pipelining multiple memory banks so that while Bank 0 is precharging, Bank 1 is sensing, Bank 2 is restoring, and Bank 3 is transferring data across the pins.

The Bridge Between Silicon and Software

Without Dynamic RAM, the modern computer revolution would have hit an insurmountable economic and physical wall:

• Processors would have remained throttled by the agonizing delay of mechanical storage.
• Software would have remained constrained to tiny programs that fit into microscopic SRAM registers.

Every line of software you write, every operating system kernel that schedules threads, and every neural network that multiplies matrices relies on this microscopic physical reality:

Billions of microscopic, femtofarad cylinders of treated silicon, endlessly losing their charge to quantum leakage, endlessly kept alive by a memory controller sweeping through thousands of rows every millisecond, and differential amplifiers catching faint 50-millivolt whispers and amplifying them into crisp, definitive ones and zeros.